1. Field of the Invention
The present invention relates to a reticle and a method of manufacturing a solid-state image sensor.
2. Description of Related Art
When a chip having a very long side such as a one-dimensional CCD (Charge Coup led Device) is to be formed, a chip larger than an exposure area of an exposure device is formed by exposing a peripheral circuit portion and a multi-repetition portion. FIG. 1 is a schematic diagram showing a typical reticle layout, and FIG. 2 is a schematic diagram showing an exposure shot map 130 on a wafer using a reticle of FIG. 1. When a solid-state image sensor is manufactured, a chip size in a longitudinal direction becomes very long as e.g. 20 nm to 80 nm particularly in a case of a one-dimensional CCD due to a number of pixels thereof and a cell size thereof. Accordingly, a chip pattern cannot be formed only by one exposure when a stepper is used. Therefore, as shown in FIG. 1, a reticle 101 is formed by providing a repetition portion (B) 112, an input portion (A) 111 and an output portion (C) 113. Here, the repetition portion (B) 112 is for a pixel portion having a repetition of the same pattern on one chip. The input portion (A) 111 and the output portion (C) 113 are for a peripheral circuit portion such as an amplifier circuit portion other than the pixel portion. Then, as shown in FIG. 2, in an exposure process, the input portion (A) 111 and the output portion (C) 113 are firstly blinded by an exposure device and only the repetition portion (B) 112 is exposed onto a wafer 120 multiple times. Subsequently, the repetition portion (B) 112 is blinded and the input portion (A) 111 and the output portion (C) 113 are exposed onto the wafer 120 simultaneously. Thus, a desired chip having a longitudinal length 149 is formed. In this example, an exposure for a one-dimensional CCD chip is carried out by four times of exposure shots of the repetition portion (B), one time of exposure shot of the input portion (A) (including an adjacent output portion (C)), and one time of exposure shot of the output portion (C) (including an adjacent input portion (A)), respectively, i.e., total six times of exposure shots.
As a related technique thereto, a manufacturing method of a solid-state image sensor is disclosed in Japanese Patent No. 2624570 B (Patent Literature 1). In this manufacturing method of the solid-state image sensor, a reticle with a chip pattern is mounted to a reduced-projection exposure device, which includes an offset device for parallel-shifting a projection coordinate and a blind device for blinding a part of the reticle, so that the chip pattern is reduced and projected to be transferred onto a wafer. In this manufacturing method of the solid-state image sensor, the chip pattern is previously divided into a plurality of drawing patterns and disposed onto the reticle. A specific drawing pattern is transferred onto the wafer under a condition that the remaining drawing patterns other than the specific drawing pattern among the plurality of drawing patterns are light-shielded by the blind device. Thereafter, under the condition that the remaining drawing patterns other than a drawing pattern adjacent to the specific drawing pattern among the plurality of drawing patterns are light-shielded by the blind device, the drawing pattern to be adjacent is adjusted in position on the wafer by the offset device so that an overlapped width between the specific drawing pattern and the drawing pattern to be adjacent thereto is increased or decreased to be brought adjacent to the specific drawing, and the drawing pattern is transferred onto the wafer.
Also, an exposure method is disclosed in Japanese Patent Publication No. JP-A-Heisei 10-189423 (Patent Literature 2). In this exposure method of a semiconductor chip, a reticle having first to third patterns formed thereon is used. This exposure method of the semiconductor chip includes: a step of exposing the first pattern of the reticle to one end of the semiconductor chip; a step of exposing two or more second patterns to the central part of the semiconductor chip in a certain direction adjacent to the exposed first pattern; and a step of exposing the third pattern to the other end of the semiconductor chip in the certain direction adjacent to the exposed second pattern.
Further, a manufacturing method of a semiconductor device is disclosed in Japanese Patent Publication No. JP-A-Heisei 06-045581 (Patent Literature 3). In this manufacturing method of the semiconductor device, a plurality of semiconductor devices having a plurality of circuit portions of different functions is made into a wafer. This manufacturing method of the semiconductor device includes: at least a first step of repeating a pattern drawing which is achieved by simultaneously exposing any number of circuit portions having a first function in the semiconductor device to thereby execute a pattern drawing of the circuit portions having the first function; and a second step of repeating a pattern drawing which is achieved by simultaneously exposing any number of circuit portions having a second function in the semiconductor device to thereby execute a pattern drawing of the circuit portions having the second function.
A pattern forming method of a charge coupled color line sensor is disclosed in Japanese Patent Publication No. JP-A-Heisei 02-121368 (Patent Literature 4). In this pattern forming method of the charge coupled color line sensor, a pattern is formed through a divided exposure. The pattern forming method of the charge coupled color line sensor is characterized in that the number of bits of a cyclic pattern portion to be formed through the divided exposure is a multiple of 12.
A reticle manufacturing method of a solid-state image sensor is disclosed in Japanese Patent Publication No. JP-A-Heisei 02-037773 (Patent Literature 5). In this reticle manufacturing method of the solid-state image sensor, a pattern for defining a shape of a repeat unit cell including at least one unit light receiving element of a light receiving portion of a solid-state image sensor is drawn by scanning an energy beam flux on a surface of a reticle so that the reticle of the solid-state image sensor is manufactured. In this manufacturing method, it is characterized that a reticle of at least one step of the reticle is manufactured while the number of the unit light receiving elements constituting the repeat unit cell is changed from a reticle in the other step.
We have now discovered the following facts. In the case of the exposure shot map as shown in FIG. 2, it is necessary to set a virtual exposure shot 148 (hatching portion) corresponding to one piece of the one-dimensional CCD chip as a fundamental step of an automatic misalignment measurement. The reason is as follows. The size of the repetition portion (B) 112, the size of the input portion (A) 111 and the size of the output portion (C) 113 are different from each other in many cases. Therefore, it is difficult to adapt the fundamental step to the sizes of the whole portions even if it is intended to execute the automatic misalignment measurement every fundamental step. Thus, the automatic misalignment measurement cannot be executed every exposure of each portion.
However, as mentioned above, if the virtual exposure shot 148 is set as a fundamental step of an automatic misalignment measurement, there may be possibly considered a case where a longitudinal length 149 of the virtual exposure shot 148 exceeds a size setting limit of an automatic misalignment measurement device, resulting in difficulty of the measurement.
Even if the longitudinal length 149 of the virtual exposure shot 148 is below the size setting limit, there may be considered a case where a misalignment measuring position on the wafer 120 is extremely restricted. For example, in the example shown in FIG. 2, one virtual exposure shot 148 includes four times exposure shots of the repetition portion (B) 112, one time exposure shot of the input portion (A) 111 and one time exposure shot of the output portion (C) 113. At this time, the automatic misalignment measurement can be executed only in any one exposure shot position of the exposure shots of the repetition portion (B) 112, the input portion (A) 111 or the output portion (C) 113 within the virtual exposure shot 148. For example, if a misalignment measurement pattern for use at a time of the automatic misalignment measurement is arranged in the repetition portion (B) 112, there exist four misalignment measurement patterns within the virtual exposure shot 148. However, since the fundamental step of the automatic misalignment measurement is set in the virtual exposure shot 148, the misalignment can be measured only in one position of the four positions. Then, measurable positions of the automatic misalignment measurement can be set only at unevenly distributed positions on the wafer 120, and there arises a problem that accuracy in misalignment compensation is deteriorated.